In a variety of consumer electronics, solid state drives incorporating non-volatile memories (NVMs) are frequently replacing or supplementing conventional rotating hard disk drives for mass storage. These non-volatile memories may include one or more flash memory devices, the flash memory devices may be logically divided into blocks, and each of the blocks may be further logically divided into addressable pages. These addressable pages may be any of a variety of sizes (e.g., 512 Bytes, 1 Kilobytes, 2 Kilobytes, 4 Kilobytes), which may or may not match the logical block address sizes used by a host computing device.
During a write operation, data may be written to the individual addressable pages in a block of a flash memory device. However, in order to erase or rewrite a page, an entire block must typically be erased. Of course, different blocks in each flash memory device may be erased more or less frequently depending upon the data stored therein. Thus, since the lifetime of storage cells of a flash memory device correlates with the number of erase cycles, many solid state drives perform wear-leveling operations (both static and dynamic) in order to spread erasures more evenly over all of the blocks of a flash memory device.
To make sure that all of the physical pages in a NVM (e.g., flash memory device) are used uniformly, the usual practice is to maintain a table for the frequency of use for all of the logical pages and periodically map the most frequently accessed logical address to physical lines. However, these table indirection based methods incur significant overhead in table size. For instance to use a table approach for a 2 terabyte (TB) storage device with 512 byte pages, a 137 gigabyte (GB) table would be needed. This is clearly not practical.